|2. Typical errors when timing constraints are neglected|
|3. Timing constraints to meet the setup and hold time|
|4. No metastability but still invalid|
Implementation process of digital circuit technology
The digital circuits of an FPGA or within the programmable area of an SoC are not programmed, but are first described by a description language such as VHDL, Verilog, SystemC or even C and then synthesized by appropriate tools. The implemented description can be a behavioral description but also a structural description.
The synthesized result then corresponds to a digital circuit, which can already be technology-specific. A simple example is the digital circuit shown in Figure 1.
Figure 1 shows that the synthesized digital circuit is within a single clock domain, since the surrounding flip-flops are supplied with a single clock (Clock A). This synchronous circuit has to be mapped to the FPGA or SoC technology by another process. In this process, the dedicated resources are reserved and connected (routed) within the programmable logic. According to Figure 1, the resources requirements are three flip-flops and a logical OR. The routing process also uses dedicated routing resources. These are located within the programmable logic in various combinations. During the entire placement and routing process, the automated tool has the following important degrees of freedom, among others:
- The required resources can be reserved at various locations within the programmable logic.
- Different routing options may be used for a reserved resource combination.
The automated tool must now perform the placement and routing using all degrees of freedom and ensure that everything is placed and connected. In addition, the most important point to note is that the setup and hold times of the flip-flops must meet the specified setup and hold times of the specific programmable logic technology. This is done under consideration of the given signal propagation delays within the digital circuit under all operating conditions.
The process for meeting the setup and hold times is also called timing closure. If these times are not met, the data transfer of a flip-flop may fail and the data output may become metastable.
Setup and hold times of flipflops
In order for a flipflop to be able to take over the signal applied to the D input (data of one bit) stably to its Q output (data output), the input signal must be applied stably and equally to the D input a certain time before any incoming relevant clock edge (setup time) and a certain time after the same clock edge (hold time). If this is not the case, there is a not negligible probability that the affected flip-flop will not be able to accept the data reliably. The data output can then become metastable (temporarily stable). Figure 2 illustrates the time requirements.
Figure 2 shows the three possible time ranges in which the input signal of a flipflop can change. Figure 2 (b) shows the critical case. If the input signal changes within this time frame, it is uncertain within a certain time frame which data the output signal will show, how long it will take to get back to a stable state and even which will be the final stable output signal. Of course, this process is strongly technology-dependent.
But it is a fact that such a metastable output signal can have fatal consequences for the digital circuit following in the data path. For example, the flip-flops following in the data path could take over completely wrong values, because the glitches (also called hazards) of the included combinatorial logic have not faded out yet. Or the following flip-flops also become metastable. Unfortunately, the probability of these errors occurring is quite low but large enough to noticeably put a digital circuit into wrong or unexpected states, because the error conditions occur several million times per second and this is only the case for a single flip-flop.
2. Typical errors when timing constraints are neglected
The concrete errors of a digital circuit caused by metastability from the application point of view are unfortunately very specific. But there are the following typical signs, which are indications for this failure class:
- A faulty behavior occurs only sometimes, i.e. randomly.
- There may also be contiguous time periods in which the faulty behavior does not occur at all, even though nothing has been changed. After that the error occurs again.
- After a small change in the FPGA design, at a point which should not affect the error situation at all, and re-synthesis, the faulty behavior occurs more frequently or is not recognizable for a short time.
- The occurrence of the error depends on the temperature of the circuit. Frankly spoken, it works in the morning but in the evening it doesn’t work anymore.
- If a different board is installed for debugging, which includes the same FPGA design, the error frequency can be of a completely different order of magnitude.
If the faulty behaviour occurs more frequently during the development phase after the replacement, this would even be GOOD. It could also happen that the faulty behaviour after the board exchange occurs unnoticed rarely with a few prototypes and then again more often during series production at the customer’s site, when several hundred units or more are produced per year. This is very BAD!
Especially with the last indication, it is obvious that this situation is unacceptable for development costs, development times and the reputation of a company. For this reason these errors should be avoided.
3. Timing constraints to meet the setup and hold time
In order to ensure that the setup and hold times of each single flip-flop in a digital circuit meet the requirements, so-called timing constraints (timing boundary conditions or specifications) are used. The concrete implementation of these constraints varies according to which data paths between which digital circuits have to be handled. In practice, four possible cases can be distinguished here based on the location of the data source circuit and the data destination circuit. These are:
- Source and destination circuit are in the same clock domain and are therefore synchronous. This case also includes situations in which the clock frequencies of the source and target circuits are different, but their temporal relationship to each other is still completely known.
- The source circuit is located outside of the programmable logic and the destination circuit inside. Since these are data inputs from the point of view of programmable logic, the so-called input timing is specified with the corresponding timing constraints. The time relationship of the relevant clock domains is completely known.
- The source circuit is inside the programmable logic and the destination circuit is outside. Conversely, from the point of view of programmable logic, these are data outputs. Therefore, the so-called output timing is specified with the corresponding timing constraints. The time relationship of the relevant clock ranges is also completely known here.
- Source and target circuit are located in different clock domains, which then can be considered as asynchronous to each other. This means that the time relationship of the clock ranges is not completely known.
For each case mentioned, appropriate timing constraints can be used to enable the automatic placement and routing process to meet the necessary setup and hold times. If these constraints are not specified, the placement and routing process generally does not take them into account, or automatically makes assumptions to complete the process that may not be correct. In this situation, setup and hold time violations usually occur during the real implementation on the board, which need not be known to the automated development tool.
Due to this reason it is important to know and apply the timing constraints and their effects in detail before a digital circuit in programmable logic is released for use. This applies no matter whether the digital circuit is developed from a higher level of abstraction from a software development environment or directly in register transfer level (RTL) based development environment for FPGAs or SoC. For the application of timing constraints, for example, the company Xilinx offers the “Xilinx Design Constraints” (XDC). These are commands based on Tcl semantics.
In the 1st case, for example, it is already sufficiently effective to specify all clock frequencies within the programmable logic and their relationship to each other. For the 2nd and 3rd case, the corresponding constraints for input and output timing can be used for specification. The 4th case is a relatively special case. For the handling of asynchronous circuits, the special constraints for specifying the clock domain relationships make less sense. Nevertheless, there are approaches which, by clever use of timing constraints and the corresponding synchronization stages (see Figure 3), make it possible to transfer data between asynchronous circuits very efficiently with low latency at maximum throughput. The latency is lower than the latency achieved by the FIFO generators of the common manufacturers because it is specially adapted to the application.
4. No metastability but still invalid
Although a careful developer can use timing constraints to reduce the probability of metastable flip-flop states to a practically negligible level, this does not mean that all signals are valid after synchronization. A typical case of such a situation is for example the synchronization of an asynchronous bus of width >1 into a digital circuit.
Synchronization stages as in Figure 3 for each individual data line resulted in a stable signal inside the circuit, but the now synchronous data of the bus (see output D in Figure 3) may be temporarily invalid. Invalid data, which are assumed to be valid by a further processing digital circuit, can of course also be a reason for serious problems.
To avoid this, there are also circuit techniques that can be implemented in the programmable logic of FPGAs and SoCs, which in combination with timing constraints provide data transfer with minimum latency at highest throughput.