Good to know
Here I would like to hand over to you important topics that should be considered for a reliable FPGA design, a flexible system architecture and an efficient algorithm implementation in programmable logic. During many projects on embedded systems, it has been shown repeatedly that neglecting these points can have serious disadvantages. The consequences for a project include an excessively prolonged development phase and development costs that are higher than expected.
Perhaps you have already made similar experiences. Select a topic to learn more …
System Architecture of Embedded Systems
This topic will take a closer look at the system architecture of embedded systems. Although the system architecture does not necessarily determine the basic functioning of a system, it does influence practical factors such as the performance, reliability or extensibility of a system and is also relevant for the smooth development and deployment of a system.
Timing constraints are a very important part of a reliable FPGA design. They enable the timing requirements of a synchronous digital circuit to be met. This process is also called timing closure. In addition, timing constraints also support reliable, efficient and fast data transmission between asynchronous digital circuit components, also known as asynchronous clock domains.
Serialize/Vectorize VHDL Records
It is often necessary to serialize VHDL records, i.e. to convert them into a vector of the type std_logic_vector. VHDL does not provide a direct method for this. This article presents a manual but nevertheless comfortable approach to convert VHDL records into vectors and vice versa with manageable effort.