timing_constraints_fig_2_en

possible time shift of the input signal of a flip-flop to its clock signal; (a) Input signal changes before the critical time period, a logic 1 is accepted stably; (b) Input signal changes during the critical time period, it is uncertain which logic level the flip-flop will accept and how long a possible metastability will last exactly; (c) Input signal changes after the critical time period, a logic 0 is accepted stably

possible time shift of the input signal of a flip-flop to its clock signal; (a) Input signal changes before the critical time period, a logic 1 is accepted stably; (b) Input signal changes during the critical time period, it is uncertain which logic level the flip-flop will accept and how long a possible metastability will last exactly; (c) Input signal changes after the critical time period, a logic 0 is accepted stably

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